Square root computer



April 1960 J. H. FELKER 2,934,268

SQUARE ROOT COMPUTER Filed May 28, 1956 7 Sheets-Sheet 1 FIG.

N- TERMINAL OR-C/RCU/T POS/T/VE X INPUTS OUTPUT SYMBOL FIG. 2

OR N-TERM/NAL AND-CIRCUIT X! x2 POS'lT/VE INPUTS OUTPUT X0 SYMBOLINVENTOR J H. FELKE'R BY ,q

.Arr R v's April 26, 1960 Filed May 28. 1956 J. H. FELKER SQUARE ROOTCOMPUTER INHIBITOR C/RCU/ 7' lNH/Bl TING PULSE 8 A=RULSE TO BE RET/MED8' D/G/ T PU LSES REFERENCE PULSES FROM MASTER CLOCK v 7 Sheets-Sheet 2INVENTOR J H. FELKER 81 .4 TTORNEV April 1960 J. H. FELKER 2,934,268

SQUARE ROOT COMPUTER Filed May 28, 1956 7 Sheets-Sheet 3 FIG. 5

STORAGE ceu. DELAfV ERASE L/ E SIGNAL 5 INH L T DATA 5 0R & OUTPUT TO BEST ORED SYMBOL DIG/T P E PULSES SC FIG. 6A

CONVERG/NG SWITCH UNIT DIG/T P PULSES SYMBOL FIG. 6B

SWITCH SU/A sum oo M b AT-S SETS SWITCH MULTlPL/ED UNITS To ERASE E 7'To OTHER SW/TC Ml/T5 A7 WITH NO A7 5 STORE s ASSOCIATED 5 WITH THESAMESETS SWITCH UNITS TO b STORAGE CELL IN TOR J FL/(ER ATTORNEY April 26,1960 J. H. FE LKER SQUARE ROOT COMPUTER Filed May 28. 1956 7Sheets-Sheet 7 SWITCH OF FIG-l0 .7 DETAILS OF SQUARE ROOT PROCESS--'CONOUCTOR NUMBERS OF FIG-l0 TIME 0 o o o O o o o 0 o o o INVBVTOR .4H. FEL/(ER A TTOPNEY SQUARE ROOT coMrUTnn Jean H. Felker, Livingston,NJ, assignor to Bell Telephone Laboratories, Incorporated, New York,N.Z., a corporation of New York Application May 28, W56, Serial No.587,568

15 Claims. (Cl. 235-158) This is a continuation-impart of my applicationSerial No. 258,448, filed November 27, 1951, for Computer Circuit, andnow abandoned.

This invention relates generally to computers and more particularly todigital computers of the variety known as serial binary computers.

More specifically, the invention disclosed and claimed hereinaftercomprises a component of a computer, or the entire computer dependingupon the scope of operations performed by same, herein referred to as asquare rooter. The invention, as its name implies, is a computing meansor machine for performing the process of extracting the square root of anumber.

A serial computer is one which handles and performs computing functionson a time basis, as distinguished from a spatial basis. That is, thefunctioning of the computer is based upon timed pulses occurring atregular intervals of time where each pulse, in the binary system ofarithmetic, designates a denominational or exponential order of a base,such, for instance, as the base 2 which is used as exemplary insubsequent discussion. Any particular number in the binary equivalent ofthe more common decimal system of notation is represented by asuccession of pulses or absences of pulses spaced in time andindentifiable as digits. Each digit of the binary number represents, ina base 2 system, successive powers of 2from up to 4, if a five-digitsystem, or up to 5, if a six-digit system, etc., depending upon how highthe exponents of the base 2 must go in order that the sum of all of suchpowers of 2 will equal the decimal number represented by the binarynotation. The presence of a 1 in a digit place indicates the presence ofone unit of that particular power of 2. The presence of a O in a digitplace indicates the absence of a unit. of that particular power of 2.The following table illustrates this relationship:

1 0 0 1 1 0 Binary Number=38 0 1 0 0 1 1 Binary Number=19 1 0 1 0 1 OBinary Number=42 In serial binary computers the binary numbers appear adigit at a time spaced at regular intervals, such as every microsecond.Thus the above decimal number 38 will appear in the computer in theorder of 01-1001, representing pulses and absences of pulses spaced atregular intervals of time from left to right. Likewise the number 19will appear as 1l00-10, the least significant digit appearing first.

It is believed that there has been no prior square rooter mechanized forhigh speed computation. The present invention mechanizes, by the use ofcircuits for handling accurately timed pulses, the arithmetic method ofextracting a square root. What is believed to be a new and basiccontribution to this art is such a computer circuit a, use

or machine including means for eliminating the necessity of making trialguesses in the arithmetic method.

As is well known, the arithmetic method of extracting a square rootinvolves the making of successive trial guesses as to the proper valueof answer digits. Such trial guesses are used to create successivesubtrahends for subtraction initially from the number and subsequentlyfrom each successive remainder. If a negative remainder is produced itis necessary, in the usual manual arithmetic method, to erase the wrongtrial guess and the negative remainder and the subtrahend and to repeatthe step using anew lower order trial digit. For machine operation in aserial computer the actual retracting of such steps is not possiblebecause by the time a negative remainder is detected the previoussubtrahends and remainders have disappeared. The present inventioneliminates the troubles associated with wrong trial guesses. The presentinvention makes an assumption that the answer digit being determined isa one but does not insert this digit 1 into the answer unless a positiveremainder is detected. If a negative remainder is detected the machinewrites a zero in the answer and then proceeds to form from the instantnegative remainder a number equal to the new next proper remainder byadding a variable but controlled set of operator digits tothe instantnegative remainder. The digits of this operator set are determined bythe significance in the answer of the digit associated with the negativeremainder.

purpose of the invention then is eliminating trial.

guess complications in the extraction of a square root and simplifyingthe operation of such a machine or computer. A feature of the inventionis the provision of means in a computer for mechanizing the arithmeticprocess of extracting a square root.

A specific feature of the invention is the provision of means in asquare rooter for eliminating the complications born out of wrong trialguesses for answer digits made in the arithmetic process of extracting asquare root.

Subsequent detailed description of an embodiment of the invention isbased upon the drawings, of which the fol lowing are generaldescriptions of the various figures:

Fig. 1 shows an OR circuit and its symbol; Fig, 2 shows an AND circuitand its symbol; Fig. 3 shows an inhibitor circuit and its symbol; Fig. 4illustrates by a block diagram the use of active I elements, such as anamplifier, for retiming purposes;

Fig. 5 is a block diagram of a storage cell and its symbol;

Fig. 6A is a block diagram of a converging type single-:

pole double-throw switch unit and its symbol;

Fig. 68 illustrates how a storage cell like that of Fig. 5 can controlone or more switch units like that of 'Fig. 6A to comprise asingle-switch unit or ganged switch units;

Fig. 7 is a block diagram of an adder and its symbol;

Fig. 8 is a block diagram of an accumulator;

Fig. 9 is a table referred to in the detailed description as an aid tounderstanding the square rooter action;

Fig. 10 is a block diagram of a square rooter; and

Fig. 11 is a table showing the exact pulse status of each conductor ofFig. 10 for each digit period of an assumed example.

The description to follow comprises two general sections. The firstsection, designated General Description, describes the content of thebasic units which are contained in the block diagrams of the squaremotor and other parts of the computer. The second section,

designated Detailed Description of Square Rooter, is,

3 GENERAL DESCRIPTION This general description covers a discussion ofthe circuitry shown in Figs. 1 through 8 of the drawings as a basis fordiscussion of the square rooter circuit shown in Fig. 10, the action ofwhich is illustrated in Fig. 9.

The or-circza't With reference to Fig. 1 an n terminal or-circuit isshown which develops an output when any one of the its input terminalsis energized by a positive pulse. The elements X X to X may be crystaldiodes or dry rectifiers or any other unidirectional asymmetric currentcarrying device which changes its impedance according to the polarity ofthe potenital across its terminal. Such elements are put in series witheach input to prevent a pulse at one input from feeding back to any ofthe other inputs. 'In the lower portion of Fig. l is shown the symbolfor this or-circuit, which symbol is used in subsequent block diagramsto simplify the showing.

The and-circuit Fig. 2 shows an and-circuit having it input terminalsand which develops an output only when all n of the input terminals areenergized by positive pulse inputs. Each of the inputs is returned to anegative voltage and the output is clamped slightly below ground by XOnly when all of the inputs rise above ground will X be cut onpermitting the output to rise. Thus, the output consists of theoverlapping parts of the input.

Two terminal and-circuits are used extensively in serial computers forretiming signals. One terminal of the circuit is fed by the signal to beretimed while the other is fed by digit pulses from a master clock.There will be an output from the circuit only for the overlap of themaster digit pulse and input signal. The circuit arrangement whereby theoutput is made a replica of the pulse from the clock is discussedsubsequently in connection with Fig. 4.

The inhibitor-circuit An inhibitor-circuit is shown in Fig. 3. Aninhibitor terminal can be added to any and-circuit or any or-circuit.Such a circuit operates as though there were no inhibitor terminal whenthe inhibiting pulse is not transmitted. When the inhibiting pulse ispresent, however, the circuit prevents any output from being developed.The inhibiting-circuit used in this disclosure is of the simple varietyshown in Fig. 3 where positive imputs synchronized in time are required.It will be noted that the signal to be inhibited is passed through aneighth digit delay line while the inhibiting pulse is passed boththrough and around a quarter digit delay line. This insures that theinhibitor pulse will, in effect, arrive earlier than the signal pulseand will last longer. In the absence of input pulses crystal X; willclamp the output at ground because input B is returned to a negativepotential. It will be noted that X and X are re turned through thetransformer to a positive potential. Elf input B goes positive (withoutan inhibiting pulse appearing on input A), X, will be cut off and theoutput voltage will rise until it is clamped at the positive potentialto which X and X are returned. If there is an inhibiting pulse(positive) it is inverted by the transformer and will carry the cathodeof X and X negative, which Will keep X conducting no matter what happensat B. Thus if pulses A and B were written as a two-digit binary numberAB, the circuit translates 01 into a 1 at the output. It translates 00,10 and 11 into at the output.

Use of active elements Active elements are shown herein as repeatingamplifiers to make up for attenuation in crystal circuits and delayline. The standard use would include a timing feature as well asamplification. This proposition is disclosed in Fig. 4.

In the design of' the computer, wherever a pulse is likely to sniferintolerable attenuation, deformation, or a variable delay, a circuitlike that of Fig. 4 is inserted.

The circuit shown has two inputs A and B. Input A is the pulse to beretimed and amplified. Input B comes from the master clock. Thiscomponent supplies reference pulses (known as digit pulses) every digittime. These pulses are available in various phases, that is, withvarious but accurately controlled delays of a fraction of a digit time.The pulse fed to B is selected to rise sometime between the expectedrises and falls of the pulses on A.

If there is no input on A, there will be no output from the amplifier Abecause of the and-circuit. If there is an input on A, when the digitpulse arrives, the amplifier output will rise with a rise timedetermined by the digit pulse (assuming that the amplifier pass handdoes not limit it). Part of the amplifier output is fed back through anor-circuit to the and-circuit. This insures that the output pulse willnot fall until the reference digit pulse does, .even though pulse A mayhave entered before B rose.

This reshaping with crystal circuits and an amplifier is the way inwhich every pulse is maintained with a desired time synchronization.Pulse A may vary somewhat in the delay it has suffered but the outputpulse will still leave the amplifier at a time determined only by the.reference pulse from the master clock. Thus the pulses in the computerare made to have fixed durations and to occur at designated times.

Delay lines, amplifiers and master clocks In the above discussionso-called delay lines have been referred to. It will be appreciated bythose skilled in the art that what is meant by delay lines is theelectrical circuit which will delay the output of an input pulse for acertain length of time. Such delay lines could comprise lumpedimpedances including successive series of lumped inductances with shuntcapacity thereacross, as is well known in the art.

The above-mentioned amplifier may comprise any elec tronic or otheramplifier arranged to amplify pulses at a high speed provided suchamplifier has sufiicient band width as above mentioned such that it willnot unduly distort leading and trailing edges of the pulses. Anamplifier which is particularly suited for use in the computer circuitdisclosed herein is disclosed and claimed in Patent 2,670,445 issued toI. H. Felker on February 23, 1954. However, any suitable amplifier willsuflice as will be readily appreciated by those skilled in the art.

Reference has been made previously to such things as a master clock andclock pulses and timing pulses. It is well known in the art that indigital computer circuits it is necessary to provide a master timingclock circuit from which pulses accurately controlled as to phaseduration and time may be derived for the purposes of controlling thevarious functions of the machine. It is not considered necessary to thecompleteness of the present disclosure for showing all of the details ofsuch a computer timing unit as the details thereof are fully within theknowledge of the art. For instance, a suitable timing unit is disclosedin a publication entitled A Digital Computer Timing Unit" by R. M.Goodman at pages 1051 through 1054 of the Proceedings of the I.R.E.,September 1951, volume 39, No. 9. Repeated reference will be madethroughout subsequent description to such master clock timing pulses andsuch reference relates to such type of circuit as is shown in the abovepublication by Goodman.

The storage cell The basic storage cell proposed herein is not a staticdevice like a flip-flop but is an electric delay line plus an amplifier.When vacuum tubes are used this type of storage saves one active elementin a one-digit storage cell and is believed to be a more reliable use ofactive elements. In larger storage units more elements will be saved.

A block diagram of such a storage cell is shown in Fig. 5. The unit hasthree inputs: digit pulses, the signal to be stored, and an erase pulse.The digit pulses are received from the master clock every digit time andare used to retime the output of the delay line before it is amplifiedand recirculated. The erase signal is received whenever new data are tobe stored and serves to erase the data in storage, blocking the delayline out-put from its input until the new data have been inserted.

The delay line may be long enough to store one word or just one digit ofdata. It is believed that up to fifteen-digit delay lines with lumpedimpedances can be built to hold the delay constant within a smallfraction of one digit time. Depending upon the length of a word, it maybe necessary to break one word line into sections and insert anamplifier between sections to retime and regenerate the pulses stored.At this point it may be stated that the retiming circuit of Fig. 4, aswell as amplifiers alone, or inhibitor circuits, may be inserted at manypoints throughout the circuits of the following description toaccomplish additional functions.

Switches A switch comprises at least one storage cell like that of Fig.5 and at least one switch unit like that of Fig. 6A, which happens to bea converging-type switch unit. A switch unit will assume a positionaccording to the output instructions from the associated storage celland the storage cell in turn is controlled by control signals whichstore therein or erase therefrom the switching instruction.

Fig. 6A shows a converging switch unit which can switch either of inputs0 and b to a converging output T, the direction of information flowbeing indi cated on the symbol as an arrow pointing to the common outputterminal T.

Switches are planned to combine a switching and a storage function. Whena switch is given instructions to go to a particular position, it goesthere and remembers that it is to remain there until unlocked by anerase signal.

Fig. 613 discloses, by means of the symbols for a storage cell andswitch units, the necessary elements of ganged single-pole double-throwswitch units. It will be obvious that if a switch is to be used as asingle-pole single-throw switch, one of the terminals a and b willmerely be disregarded; that is, not connected.

A single-pole double-throw switch, such as the unit consisting of Sci"and SUlA shown in Fig. 6B, consists of a storage cell and a switchunit. When a l is stored in the storage unit, as the result of a pulseon a switching instruction lead, the left-hand and-circuit of the switchunit will pass signal a while the inhibitor blocks signal b. When a O isstored, the and-circuit will block signal a and the inhibitor circuit inthe switch unit will pass signal b.

Whenever the switch is to be reset the erase signal is sent to thestorage unit which then drops its old instruction and goes to positionb, unless the new instruction sets it to a. A double-pole double-throwswitch, as shown in Fig. 63 consisting of 8G1 and SUlA and SUlB, wouldhave two switch units and one storage unit. A three or four-pole switchwould have three or four switch units, one storage unit and perhaps anextra amplifier to prevent the switch units from loading down thestorage unit excessively. Such use of additional switch units with thesame storage unit has been indicated in Fig. 613 by the multipleentitled Multipled to 6 Other Switch Units Associated With the SameStorage Unit.

If it were desired to use a diverging switch unit, the

same circuitry as Fig. 6A may be used with slight modification. The aand b terminals of Fig. 6A would be connected together to a singleterminal marked T, which would then comprise a single input to theswitch unit. The inhibitor circuit would be disconnected from theor-circuit and connected to its own separate or, and, and amplifierarrangement. The terminal T of Fig. 6A would be designated a and thecorresponding terminal of the other or, and, and amplifier arrangementfor the inhibitor would be designated b. The single input T would thenbe switched to either the a or the 1) output depending upon whether ornot the P terminal carried a pulse. The symbol for a diverging switchunit would be the same as the symbol for the converging type, as shownin Fig. 6A, except that the arrow would be reversed.

Handling of negative numbers he last digit place of every number may bereserved to indicate the sign of the number. Positive numbers may have a0 in the last place. A negative number is obtained by taking the twoscomplement of the positive number. This results in every negative numberhaving a 1 in its last place.

This system is equivalent to the tens complement method used in decimalcalculators. In the decimal calculator operating with three significantfigures, a fourth place may be provided for the sign. The number -187might be represented by its tens complement 9813. Then, for example, if-187 were required to be added to 500, the operation would be to add9813 to 500 which gives 10313 and this is recognized as 0313 since themachine is assumed to have only four digit places.

As indicated above a negative number (twos complement) can be obtainedin the binary computer by first forming the ones complement (changingall zeros to ones and vice versa by means of an inhibitor-circuit) andthen adding one. The calculations illustrated below show examples ofbinary arithmetic performed with negative numbers.

Formation of negative numbers 0 0 1 0 0 0 Ones Complement: 1 1 0 1 1 Idone 1 .'.8= 1 1 1 0 0 0 Check 8+8= 0 +8= 0 0 1 0 0 0 8= 1 1 1 0 0 0Sum= 1 0 0 0 0 0 0=zero Tothemachine Addition 8+5=-3 1 1 1 0 0 0 +5= 0 00 1 0 1 Sum= 1 1 1 1 0 1=3 Oheck+3= 0 0 0 0 1 1 Sum= 1 0 0 0 0 0 O=zero8+15=7 8= 1 1 l 0 0 0 +15= 0 0 1 1 1 1 Sum= 1 0 0 0 1 1 1=7 The adderThe adder can be considered as a translator with three inputs: addend,augend and carry. It is a simple translator in that its output is afunction only of the number of ones among its: three inputs, as can beseen from the table set forth below:

BINARY ADDITION Inputs Outputs Addend Augend Carry Sum New Carry Theblock'diagram of a typical adder is shown in Fig. 7 wherein thecombination in the above table of 0 0 0 is automatically taken care ofas a 0 output with 0 carry. The three dashed circuits at the left of theblock diagram recognize the other three situations among the threeinputs. The situations are: at least one l," at least two 1s and threels among the inputs. If there is only one 1 it will go through thebottom orcircuit, the following inhibitor-circuit, and then anotheror-circuit. After being reclocked and amplified it will provide a 1 asthe sum. In this case none of the and-circuits on the A, B and carryleads will have operated. If there are at least two ls on the A, B andcarry. leads, at least one of the three two-terminal andcircuits in thedashed box will operate, with two results. The output of thethree-terminal or-circuit at the bottom left of the diagram will beinhibited so that it makes no contribution to the sum. In addition, acarry signal will be developed which is delayed one digit, reclocked andamplified to serve as the carry for the next augend and addend. If thereare three ls the three-terminal and-circuit at the top and left-handside of the diagram will operate and will develop a number 1. The threetwo-terminal and-circuits on the left of the diagram will also operateand will provide the carry.

The inhibitor-circuit in series with the: carry lead should be noted.This circuit may be fed by a word pulse from the master clock as well asby the carry digits. The Word pulse is received in synchronism with thefirst digit of every word. The word pulse will inhibit the carry pulseif one is present and will prevent a carry developed in one problem frombeing used in the next. This feature is required in the addition ofnegative numbers.

The carry lead may be brought outside the adder to facilitatesubtraction. Suppose X is to be subtracted from Y. The number Y might befed to the augend terminal and the number X fed through aninhibitor-circuit to the addend terminal. The inhibitor would also befed by digit pulses from the master clock and the addend would thereforebe the ones complement of X. A one would be inserted into the carryterminal in synchronism with the first digits of Y and of the onescomplement of X. The sum out of the adder would then be X Y. The adderproduces a sum within a fraction of a digit time after it receivesinput. Thus there is only a small delay in obtaining the sum of twonumbers.

The accumulator The block diagram of an accumulator is shown in Fig. 8.The output of the adder is sent back to its input through a W digitdelay line. The output of the delay line is continuously reclocked inthe and-circuit in accord with digit pulses from the master clock. Thetimed pulses are then amplified in a one-stage amplifier to make up forattenuation in the delay line. Whenever a new accumulation is to bestarted, an erase signal is sent to the inhibiting circuit. This signalis W digits long and blocks the output of the delay line from the adderand insures that the new accumulation will start frornl).

DETAILED DESCRIPTION OF SQUARE ROOTER The square root circuit is shownon the block diagram in Fig. 10 and is arranged to obtain the squarerootof a number to W places in 2W digit times. It mechanizes theordinary arithmetic method of taking square roots. Before describingthis unit it is well to consider the algebraic basis of the arithmeticmethod normally used.

Development of operating principles In the development shown below anarithmetic problem is solved in the right-hand column and thejustification for each step is shown in the left. It is to be noted thata new digit place is obtained in each step and that the only processesinvolved, apart from adding zeros, are multiplication by a number lessthan ten and subtraction.

Algebraic procedure Arithmetic procedure Find 42 F1110 (123,004

Step 1: Step 1:

Make first estimate h h =300 and obtain first remainder.

33904: R Step 2: Step 2:

Make estimate or increment Find kg such that In such that hz(2h +h2) Rh2(600+ 2) 33904 and compute second remainder. 5DX600=30, 000

1404=R Step 3: Step 3:

Find hi such that Find In such that h=[2(h +hi)+h3l R: hs(2X-350+ha)$1404 and compute third remainder 2X700=1400 Ra=Rzila[ (h1+ 2)+ s] ryhs=2 2(700-l-2) =1404 [Norn.-R3=n: (b -Ht2+hs) 1202 diam-n+0; h.

The above arithmetic method can be extended to binary operation as shownin the development below. Binary operation is somewhat simplifiedbecause the only processes needed besides adding zeros, aremultiplication by one or zero and subtraction.

Find square root 1101001001 In 02 ha in s For square root machineoperation, there is a drawback to the method illustrated immediatelyabove. Sometimes, as in the fourth step, the subtrahend must bemultiplied by 0, not 1, before it is subtracted. The only way themachine can find out it should have multiplied by O is for it to assumeit should multiply by 1, form the subtrahend on that assumption, andsubtract it. If the machine obtains a negative remainder it knows thatit should not have subtracted anything at all. The simplicities ofbinary arithmetic make it possible to devise a method of operation inwhich the necessity of adding back the subtrahend is avoided. Thisprocedure is believed to be a basically new contribution to the art.

Suppose, with reference to the algebra of the above set forth arithmeticprocedure, that the machine is taking the square root of x and has justestablished the partial answer and is about to determine the value ofh,,, where h will be either a 1 or a 0 multiplied by 2 where p is aninteger. The partial answer y,, is the sum of a number (n-l) of binaryorder increments h h etc. to h,, where each increment h is a one (1) ora zero (0) and represents respectively a different integral power of two(2) or nothing. The treatment assumes that the nth increment is about tobe ascertained and the fact is that h will be either a one (1) or a zero(0) and that it will, if a one (1), represent a power of two (2)depending upon the order of that nth position in the an swer. Forinstance, if the answer y is going to be a six-digit binary number110011, then 11 is 1, k is 1, k is 0, I1 is 0 and the nth increment (hwill be a 1. Furthermore, It, represents one times 2 I2 represents onetimes 2 h represents zero times 2 12 represents zero times 2 and k willrepresent one times 2 The letter p is the power of two (2) representedby k that is, in the example p is 1 and the n+lth increment h (or k whenascertained, will represent 2 or 2.

At this stage the remainder in the machine is and the next operationwill be to form the trial subtrahend and to subtract it from R,, whichwill leave as the new remainder If R is a positive number, the machinewill enter a 1 as the coefiicient of 2 in the answer and will proceed toobtain the coefiicient of 2 in a similar manner.

If, on the other hand, R turns out to be negative, the machine shouldwrite 0 as the coefiicient of 2 in the result (thus y =y,, and shouldsubtract Unfortunately, the machine does not have R,, available becauseit has subtracted and obtained R,,. However, to get the desired R,, themachine need only add to the erroneous R instead of subtracting whichwould have been done if R had been positive. This result is justified bythe steps set forth next.

10 If R is positive, insert 1 as the coeflicient of 2 and proceed with anew trial subtrahend (2y,,+2 )2 n+1= n( yn+ =a; y 2 2n-1 22(p1) (@lnl2lZ+1 but, if R is negative, then insert 0 as coeflicient of 2 whichmeans that y =y and the new remainder R is shown as Looking at n+l n+ n+121-1 and R may be obtained by adding [2y,,+3(2 )]2 to R (now in themachine) instead of subtracting the usual trial subtrahend (2y,,+2 )2from R,, (which was eliminated in determining the negative R There isonly a slight difference in the two operators above. When a positiveremainder is obtained, the machine adds 01 times 2 to 2y and then adds 2zeros at the end of the sum to obtain the new operator. the event that anegative remainder is obtained, the machine adds 11 (3) times 2 to 2yand then adds Z zeros at the end of the sum. Below are given twoexamples of the simplified method:

11101 =resu1t=29 The square root machine shown in Fig. 10 obtains a newdigit of a W digit answer every 2W digit times. In each 2W period themachine either substracts or adds, depending on whether the digitdetermined in the previous period is a. 1 or a 0. The remainder becomesthe next minuend, if positive, or the next augend, if negative. Therespective next subtrahend or addend is formed partly from the answerdigits already obtained and is formed therefrom into one of twooperators depending upon whether the remainder was positive or negative.The manner of forming the operator is dependent upon the value of thedigit determined in the preceding step as is the decision as to whetherthe operator is added or subtracted.

Before going into a discussion of the block diagram it is well toconsider in detail how the square root of a specific number would betaken. For this purpose a relatively short number is more convenientthan a larger one. In Fig. 9 the above last set forth example ofsimplified binary square rooting (for which W=5) has been rearranged inthe sequence in which the digits would be operated upon by a machine. Asshown in Fig. 9, the top row lists the time (measured in digit timesfrom the start of the problem) at which the digits listed arrive. Thesecond row lists the digits of the operators that are used either asminuends or augends. The third row lists the digits that make up theoperators used as subtrahends or addends. The fourth row shows theresults of subtracting or adding the operators above, and the next rowshows the answer digits as they are obtained. The final row shows whenthe answer digits are required to reappear in order to be used in thethird row.

As Fig. 9 shows, in the first period the first operator is the number(of 2W digits=10) whose square root is desired, while the secondoperator is a I inserted at digit time 2W1 (9). The last digit of theremainder is examined at time 2W (10). Since the digit examined is a 0(positive remainder), C is'written as 1, the most significant digit ofthe answer. If the 2Wth digit were 1 (negative answer), 0 should bewritten in the answer as the coeflicient of 2W. Since in the example Cis written as 1, the remainder of the first step is used as the minuendfor the next period. The subtrahend for the next period is formed by thedigit C (time10) delayed 2W--1 (9) digit times so that it arrives atdigit time 19 and by the 1 subtracted in period one (time 9) delayed by2W2 (8) digit times so that it arrives at digit time 17. The digit C wasa 1, so in the second period subtraction is performed and the 2Wth digitof the remainder examined. This digit is seen to be a 0, so theremainder obtained on the second 2W period is used-as the minuend forthe third period and a 1 is written in the answer asC The subtrahend forthe third step is formed from the digit C (time 19) delayed 2Wl (9)digit times so that it arrives at digit time 28, the digit C (time 20)delayed by 2W3 (7) digit times so that it arrives at digit time 27, anda 1 delayed 2W-2 (8) digit times from the time 17 it was used in step 2to arrive at digit time 25.

The remainder of the third step has a 1 in the 2Wth place, indicating itis negative. ,The remainder is, therefore, used as the augend for thefourth 2W period and a 0 is written as C The addend for the fourthperiod is formed by delaying the number C C (times 28 and 27) by 2W1 (9)digit times from the time it was used previously so as to arrive atdigit times 37 and 36, by delaying digit C (time 30) 2W5 (5) digit timesso that it arrives at time 35, and at digit times 33 and 34 writingones. The 1 at time 33 is the one previously written at time 25 delayedby 2W2 (8) digit times. The 1 written at time 34 is written because theremainder of the third period was negative and is the 1 written at time33 delayed 1 digit time.

From Fig. 9 it is seen that the sum in the fourth step is stillnegative. The sum is used as the augend for the fifth step and another 0is written in the answer as C The addend for the fifth step is formed bythe word C C C (times 37, 36 and 35) delayed by 2W-1 (9) digit timesfrom the time it was used in the fourth step so as to arrive at times46, 45 and 44, the digit C (time 40) delayed by 2W7 (3) digit times sothat it arrives at time 43, and the word 11 delayed by 2W2 (8) digittimes from the time (times 34 and 33) it was used in the fourth periodso as to arrive at times 42 and 41. The 1 (time 33) is delayed 2W2 (8)digit times so as to arrive at times 41 and the 1 at time 42 is the 1 attime 41 delayedl digit time. When this addend is added, the 2Wth digitof the sum is a 0, the sum is zero indicating completion of the problem,and a 1 is written in the answer as C Rules for operation of square rootmachine The procedure can be generalized as the following rules forusing the adder to obtain the square root of x, where the square root iswritten as C C C C etc., and each coeificient is a 1 or a O. In thefollowing discuscussion, the terms minuend and augend mean the sameoperator and the terms subtrahend and addend" mean the same operator.-This is because sometimes the machine performs actual addition while atother times actual subtraction takes place-but the subtraction isaccomplished by complementary addition.

Rule J.Examine every 2Wth digit of the output of the adder, and if theexamined digit is 0, write 1 as the answer digit. answer digit.

Rule 2.--In the first 2W period, use x as the augend. In all otherperiods, use the output of the adder (see Adder of Fig. 10) delayed by2W digit times as the augend.

Rule 52-211 the first 2W period form the addend for the adder by takingthe 2s complement of a number that consists of a single one written atdigit time 2W1. In

all other periods determined the addend according to ,times from its usein the previous step.

If the examined digit is 1, write 0 as the (b) The digit C,, delayed by2W+32n from the time it was obtained in the previous step.

(c) The digit 1 written two digits earlier than C,,

Rule 6.--Form the addend for the nth period from the three parts listedbelow:

(a) The same as in rule 5.

(b) The same as in rule 5.

(c) The same as in rule with an extra 1 inserted at digit time 2W+22 ofthe nth 2W period.

The block diagram One way of studying the block diagram of Fig. is totake each of the rules stated above and see how they are implemented. Inthis connection, reference is suggested to Tables 1, 2 and 3 at the endof the specification and to Fig. 11. These aids will show exactly howthe circuit satisfies these rules for an assumed example.

RULE 1 The machine receives a pulse every 2W digits on conductor 2 fromthe master clock. This pulse goes to the inhibitor-circuit that isconnected to the output of the adder. The inhibitor, therefore, examinesevery 2Wth digit of the adder output and develops a 1 on conductor 11 ifthe adder output digit is 0 and develops a 0 on conductor 11 if theadder output digit is a 1. Thus the successive output digits of theinhibitor at conductor 11 can be taken as the successive digits of thesquare root of x. Each output of the inhibitor is stored temporarily ina one-digit storage cell (DL7, etc.) until it can be written into DL4,which stores the complete answer.

The examining pulse that occurs every 2W digits also goes to theinhibitor in the one-digit storage cell to act as the erase signal,thereby to remove C when C is stored. That is, at the second examinetime (4W) the 2W examine pulse on conductor 2 will inhibit therecircultaing previous answer digit on conductor 22, thereby to permitwhatever is on conductor 11 at that time to enter DL7 without conflictwith any previous pulse.

During the first 2W period, SUI is in position a due to a start pulse onconductor 1 at time 1 having signaled the storage cell SCl to thateffect coincident with the insertion of time 1 of the least significantdigit of x into the machine on conductor 6, and the augend for the adderis x transmitted over conductor 6 through this position to conductor 8.Thereafter, SUl is at b and the augend on conductor 8 is the adderoutput on conductor 9 delayed by 2W digits in DL1 to appear on conductor27. SU1 is sent to the b position at time 2W+1 (time 11) when the 2Wexamine pulse on conductor 2 at time 10 is delayed by one digit in DLlOso as to appear on conductor 3 at time 11 to send an erase signal to thestorage cell 801.

RULE '3 Coincidentally with the transmission of the least significantdigit of x into the machine at time 1, a start signal is received fromthe master clock on conductor 1, which sends SU2 to position a bysending a store signal to SC2 through an or-circuit and over conductor14. The start signal on conductor 1 also progresses through aneight-digit delay in DL2 to arrive on conductor 4 at aninhibitor-circuit feeding conductor 28 at time 2W1 (9). The pulse onconductor 28 extends through an or-circuit to conductor 17 where itinhibits the digit pulse on conductor 7. The latter inhibitor-circuithas an output on conductor 15, therefore, which is the 1s complement of01000 0. This is because conductor carries all digit pulses fromconductor 7 except when there is a pulse on conductor 17. To convertthis to a 2s complement, the start signal on conductor 1 is fed directlyto the carry terminal of the adder through an or-circuit to conductor10. The machine cannot subtract in fact,

so, wherever subtraction is to occur it is necessary to change thesubtrahend (or addend) to the 2s complement and add. This in effect isthe same as subtraction, as has been discussed above under GeneralDescription. The 10111 1 fed over conductor 15 to terminal a of switchunit SU2 is transmitted therethrough and over conductor 18 to the lowerleft input of the adder of Fig. 10. Simultaneously with the digit time1, the start pulse on conductor 1 is fed through an or-circuit (feedingthe carry terminal of the adder) to the carry terminal of the adder onconductor 10. The net effect of adding the carry 1 to the 10111 1 is tochange the latter to 11000 0, which is the 2s complement of the desiredaddend (or subtrahend). Thus, the desired subtrahend (or addend) ischanged into its 2s complement in order that addition can be used toaccomplish a subtraction function.

The operating instructions for switch SU2 are obtained from theinhibitor in the adder output on conductor 11 as well as from the startsignal on conductor 1. SU2 is of the type discussed above under theGeneral Description of Switches. Every time'a new digit of the answer isdetermined at conductor 11, it is fed over conductors 12 and 14- to theinput terminal of the storage cell (through a one-digit delay line DL12and through an or-circuit which isolates the start pulse on conductor 1from the inhibitor output on conductor 11) associated with the switchSU2, which is adjusted at time 2W-l-1, etc. to a if the digit onconductor 14 is a l or to b if the digit on conductor 14 is a 0.Coincidentally with the existence at time 2W+1 on conductor 14 of theanswer digit, the 2W pulse on conductor 2 delayed one digit time in DL10is fed over conductor 3 to the erase terminal of the storage cell 8C2for switch SU2 to remove at time 2W+1 the previously stored instruction,so that the switch can move to the new position if such is dictated.Setting switch SU2 to w is equivalent to saying, follow rule 5 andsetting switch SU2 to b is equivalent to saying follow rule 6.

RULE '5 When digit C is determined on conductor 11 at time 2W, it goesover conductor 24 into the one-digit delay line DL7 and recirculatesthere until C is determined. The recirculation of the digit C takesplace over conductors 2 2 and 23 so long as a pulse does not appear onconductor 2 to inhibit the recirculating digit. This inhibiting takesplace at each occurrence of the 2W examine pulse on conductor 2, therebyinhibiting the recirculating C digit when C is determined on conductor11. At time 2W+1 (11) the start signal on conductor 1 delayed 8 digitsin DL2 and 2 digits in DL6 appears on conductor 5. It is inhibited,however, from reaching conductor 21 by the 2W pulse on conductor 2delayed one digit in DL10 and arriving at conductor 3 at 2W+1 (11). Therecirculated start signals from DL2 and appearing on conductor 4 are alldelayed two digits by DL6 and reappear at the output of DL6 on conductor5 in each 2W period at the times listed below:

Digits Period Time Entered in DL4 2W+1 (11) None 4W-1 (19) Cl 12W-9 (51)Us The output of DL6 on conductor 5, in each case above except the first(when it is inhibited), goes via conductor 21 to an and-circuit in theone-digit storage cell and letsa digit of the answer into DL4 overconductors 25 and 16. The input of DL4 on conductor 16 is also fedthrough the a position of switch SU3 to conductor 33, through anor-circuit to conductor 17, through an inhibitor to the a input of SU2via conductor 15, and back to the adder to mechanize part b of rule 5.The start pulse on conductor 1 at time 1 sets switch SU3 at a and theswitch remains at :1 until time 51 where the coincidence of pulses onconductors 3, and 30 sends it to b. Since C first enters DL4 at 4W-1(19) it will reenter it after 9 digits delay in DL4 at 6W-2 (28) justbehind the first entry of C; at 6W-3 (27), which is as it should be tofulfill part a of rule 5.

Part c of rule 5 is fulfilled by the recirculated start pulse from DL2on conductor 4 and which appears at times 9, 17, 25, 33, 41 and 49.Conductor 28 will also carry this pulse at the same times except at time49 when an inhibiting pulse appears on conductor 29. These pulses onconductor 28 appear on conductor 17 through an or-circuit. It may benoted that DL6 provides the two-digit delay required between C,, and the1 digit of part c of rule 5. That is, DL6 provides a pulse on conductor5 two digits later than conductor 4 and this pulse on conductor 5,occurring at times 11, 19, 27, 35 and 43, appears also on conductor 21and permits the previously determined answer digit on conductor 22 toextend through an or-circuit to conductor 16 and through the a positionof switch SU3 to conductor 33, thus feeding conductor 17.

The inhibitor at terminal a of SU2 will provide on conductor the 1scomplement of Q on conductor 17 (see rule 5). The 2s complement isobtained by feeding the output of the inhibitor on the adder output atconductor 11 back into the carry terminal at conductor 10 of the adder.The one-digit delay line (DL9) is required to get the carry onconductors 13 and 10 at 2W-l-1 (11) rather than at 2W (10).

noun 6 Parts (1" and b of this rule are fulfilled by the connection ofthe input of DL4 on conductor 16 through SU3 to conductor 33 and toconductor 19 through an orcircuit into terminal b of SU2. Part 0 isfulfilled by the connection of the output of DL2 into terminal 12" ofSU2 through an or-circuit, both directly and through the one-digit delayline. DL8. The pulses on conductor 28 at times 9, 17, 25, 33 and 41 alsofeed conductor 12 through the or-circuit. Also, conductor 20 feedsconductor 19 the same pulses one digit later at times 10, 18, 26, 34 and42.

At time 51, pulses appear on conductors 3, 5 and 30. This causes a pulseto appear on conductor 21 (via an and-circuit 'frorn conductors 5 and310) to permit the fifth answer digit into conductor 25 and thence intoconductor 16 just one digit time ahead of the other four answer digitsemerging from DL4 on conductor 26. Also a pulse will appear on conductor31 (via an and-circuit from conductors 3, 5 and thereby switching theunit SU3 to its b position. This permits the five answer digits toemerge onto conductor 32 as follows 1l001-- giving the square root of x.

Fig. 11 also indicates the position of switches Table 1.-Switchconditions of Fig. 10

Switch Explanation SU1. Directed to position 0" whenever conductor 1carries a p se.

. Directed to position "b whenever conductor 3 carries a pulse andconductor 1 does not.

Remains in the position to which it is directed until it is directed tothe other position.

Directed to position a" whenever conductor 14 carries a p se.

Directed to position 0" whenever conductor 3 carries a pulse andconductor 14 does not.

Remains in the position to which it is directed until it is directed tothe other position.

SU3 Direizted to position it whenever conductor 1 carries a u se.

SU3 Directed to position "0" whenever conductor 81 carries a pulse andconductor 1 does not.

SU3 Remains in the position to which it is directed until it is directedto the other position.

Table 2.-Pulse conditions of conductors ofFig. I0

Conductor Explanation Pulse only at digit time 1.

Pgse igng at every tenth digit time; l.e., digit times 10, 20,

Conductor 2 delayed one digit; i.c., times 11, 21, 31, 41, 51.

Conductor 1 delayed eight digits and recirculated every eight dlgits;i.e., times 9, 17. 25, 33, 41, 49.

Conductor 4 delayed two digits; i.e., times 11, 19, 27, 35, 43,

a pulse.

Pulse only when conductor 2 carries a pulse and conductor 9 does not.

Conductor 11 delayed one digit.

. Conductor 11 delayed one digit.

Pulse p nly when at least one of conductors 1 and 12 carries a pn e.

Opposite of conductor 17 (1.e., the ones complement of conductor 17Pulse only when at least one of conductors 25 and 26 carries a pulse.

Pulse uclinly when at least one of conductors 28 and 33 carries a p se.

0913111101701 15 if SU2 is at. a. Conductor 19 if SU2 is at:

Pulse only when at least one of conductors 20, 28 and 33 carries apulse.

Conductor 28 delayed one digit.

Pulse only when conductor 5 carries a pulse and conductor 3 does not.

Conductor 24 delayed one digit.

Pulse only when conductor 22 carries a pulse and conductor 2 does not.

Pulse cmly when at least one of conductors 11 and 28 carries a pn se.

Pulse only when each of conductors 21 and 22 carries a pulse.

Conductor 16 delayed nine digits.

Conductor 9 delayed ten digits.

Pulse only when conductor 4 carries a pulse and conductor 29 does not.

. Conductor 2 delayed nine digits.

Conductor 29 delayed two digits.

Pulse only when each of conductors 3, 5 and 30 carriese pulse. Conductor16 when SU3 is at; b. N othmg when SU3 15 at y, Condigctor 16 when 5173is at (1. Nothing when SU3 is at ii T able 3.-Preferred order ofconductor and. switch unit consideration of Fig. 10

Conductor Explanation Conductors 1, 2, 3, 4, 5, 7, 20, 21, 28, 29, 30,and 31 are fixed.

Conductor 6 is the number X whose square root is desired.

Switch SUI positions are fixed by conductors 1 and 3.

Switch SU3 positions are fixed by conductors 1 and 31.

Conductor 8 is conductor 6 when SUl is at; a and is conductor 27 whenSUI is at; b.

one digit earlier.

Conductor 14 is determined by conductors 12 and 1.

Switch SU2 positions are fixed by conductors 3 and 14.

Conductor 10 is determined by conductors 1 and 13 and by any internal"carry of the adder.

COIldfilOlIOI 22 is fixed by what conductor 24 was one digit ear er.

Conductor 23 is determined by conductors 22 and 2.

Conductor 25 is determined by conductors 21 and 22.

Conductors 12 and 13 are fixed by what conductor 11 was i7 Table3.Preferred order of conductor and switch unit consideration of Fig.10Continued Conductor Explanation Conductor 16 is determined byconductors 25 and 26.

Condlnctor 261s fixed by what conductor 16 was nine digits ear ier.

Conductors 32 and 33 are determined by conductor 16 and the position ofSU3.

Conductor 17 is determined by conductors 28 and 33.

Conductor 15 is the opposite of conductor 17.

Conductor 19 is determined by conductors 20, 28 and 33.

Conductor 18 is determined by conductors 15 and 19 and the position ofSU2.

Conductor 9 is the digital sum of conductors 8, 10 and 18.

condluctor 27 is fixed by what conductor 9 was ten digits ear 1er.

Conductor 11 is determined by conductors 2 and 9.

Conductor 241s determined by conductors 11 and 23.

In all discussions above it has been assumed that x is a 2W digitnumber. This may not be the case in some computers. To convert x into a2W number it may be delayed W digits, which adds W zeros to it. Thedelay may be obtained to a tap in BM. Another expedient could be to takex as a W-digit number and send the first 2W pulse at time W, the secondat 3W, etc.

It is to be understood that the above-described arrangements are merelyillustrative of the application of the principles of the invention. Forinstance, simplifications may be effected in the block diagram of Fig.10 without afiecting the functioning of the invention. As an example,conductors 12 and 13 of Fig. 10 carry the same pulse information and oneof the delay lines DL12 and D13 could be eliminated so as to makeconductors 12 and 13 in fact the same conductor. For illustrativepurposes it is believed helpful to separate the conductors 12 and 13 toperhaps clarify the two functions performed by these conductors. Otherchanges, modifications and simplifications may be devised by thoseskilled in the art without departing from the spirit and scope of theinvention.

What is claimed is:

1. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendsand for forming electrical signals representing digits of successiveinstant remainders by subtracting said instant subtrahend signalsrespectively from said number signals and from successive said instantremainder signals where said forming functions are all based uponsuccessive assumed instant digits of 1 for said answer, means fordetecting whether said instant remainder signals represent positive ornegative remainders, and means responsive to the detection of an instantpositive remainder for storing an electrical signal representing aninstant digit 1 in said answer storing means and for permitting theabove process of forming instant subtrahends and instant remainders toproceed and responsive to-the detection of an instant negative remainderfor storing an electrical signal representing an instant digit in saidanswer storing means and for forming from said instant negativeremainder signals electrical signals representing an X digit numberequal to the proper next instant remainder commensurate. with theinstant stored answer digit of 0.

2. In a binary digital computer, a square rooter for extr'acting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendsand for forming electrical signals rep resenting digits of succesiveinstant remainders by subtracting said instant subtrahend signalsrespectively from said number signals and from succesive said instantremainder signals where said forming functions are all based uponsuccessive assumed instant digits of 1 for said answer, means fordetecting whether said instant remainder signals represent positive ornegative remainders, means responsive to the detection of an instantpositive remainder for storing an electrical signal representing aninstant digit 1 in said answer storing means and responsive to thedetection of an instant negative remainder for storing an-electricalsignal representing an instant digit 0 in said answer storing means, andmeans responsive to the detection of an instant negative remainder forforming from said instant negative remainder signals electrical signalsrepresenting an X digit number equal to the proper next instantremainder commensurate with the instant stored answer digit of 0.

3. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendsand for forming electrical signals representing digits of successiveinstant remainders by subtracting said instant subtrahend signals fromrespectively said number signals and from successive said instantremainder signals where said forming functions are all based uponsuccessive assumed instant digits of 1 for said answer, means fordetermining whether said instant remainder signals represent positive ornegative remainders, means responsive to the detection of an instantpositive remainder for storing an electrical signal representing aninstant digit 1 in said answer storing means and for permitting theabove process of forming instant subtrahends and instant remainders toproceed, and means responsive to the detection of an instant negativeremainder for storing an electrical signal representing an instant digit0 in said answer storing means and for forming from said instantnegative remainder signals electrical signals representing an X digitnumber equal to the proper next instant remainder commensurate with theinstant stored answer digit of 0.

4. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendswhere said forming function is based upon successive assumed instantdigits of 1 for said answer, means for forming electrical signalsrepresenting digits of successive instant remainders by subtracting saidinstant subtrahend signals respectively from said number signals andfrom successive said instant remainder signals,

means for detecting whether said remainder signals rep-' resent positiveor negative remainders, means responsive to the detection of an instantpositive remainder for storing an electrical signal representing aninstant digit 1 in said answer storing means and responsive to thedetection of an instant negative remainder for storing an electricalsignal representing an instant digit 0 in said answer storing means, andmeans responsive to the detection of an instant negative remainder forforming from said instant negative remainder signals electrical signalsrepresenting an X digit number equal to the proper nex't instantremainder commensurate with the instant stored answer digit of 0.

5. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendswhere said forming functionis based upon successive assumed instantdigits of l for said answer, means for forming electrical signalsrepresenting digits of successive instant remainders by subtracting saidinstant subtrahend signals respectively from said number signals andfrom successive said intant remainder signals, means for detectingwhether said remainder signals represent positive or negativeremainders, means responsive to the detection of an instant positiveremainder for storing an electrical signal representing an instant digit1 in said answer storing means and for permitting the above process offorming instant subtrahends and instant remainders to proceed, and meansresponsive to the detection of an instant negative remainder for storingan electrical signal representing an instant digit in said answerstoring means and for forming from said instant negative remaindersignals electrical signals representing an X digit number equal to theproper next instant remainder commensurate with the instant storedanswer digit of O.

6. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendsand for forming electrical signals representing digits of successiveinstant remainders by subtracting said instant subtrahend signalsrespectively from said number signals and from successive said instantremainder signals Where said forming functions are all based uponsuccessive assumed digits of 1 for said answer, each instant subtrahendbeing of fixed signal content depending upon the significance of theassociated assumed instant digit in said answer, means for detectingwhether said instant remainder signals represent positive or negativeremainders, means responsive to the detection of an instant positiveremainder for storing an electrical signal representing an instant digit1 in said answer storing means and responsive to the detection of aninstant negative remainder for storing an electrical signal representingan instant digit 0 in said answer storing means, and means responsive tothe detection of an instant negative remainder for forming from saidinstant negative remainder signals electrical signals representing an Xdigit number equal to the proper next instant re mainder by adding tosaid instant negative remainder signals electrical signals representinga special set of digits where the digit content of said set isdetermined by the instant associated significant digit of 0 in saidanswer.

7. In a binary digital computer, a square meter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe a square root of said number as the answer, means for formingelectrical signals representing digits of successive instant subtrahendsWhere said forming function is based upon successive assumed instantdigits of l for said answer, each instant subtrahend being of fixedsignal content depending upon the significance of the associated assumedinstant digit in said answer, means for forming electrical signalsrepresenting digits of successive instant remainders by subtracting saidinstant subtrahend signals respectively from said number signals andfrom successive said instant remainder signals, means for detectingwhether said instant remainder signals represent positive or negativeremainders, means responsive to the detection of an instant positiveremainder for storing an electrical signal representing an instant digit1 in said answer storing means and responsive to the detection of aninstant negative remainder for storing an electrical signal representingan instant digit 0 in said answer storing means, and means responsive tothe detection of an instant negative remainder for forming from saidinstant negative remainder signals electrical signals representing an Xdigit number equal to the proper next instant remainder by adding tosaid instant negative remainder signals electrical signals representinga special set of digits where the digit content of said set isdetermined by the instant associated significant digit 0 in said answer.

8. In a binary digital computer, a square meter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingsuccessive instant series of electrical signals representing successiveinstant series of X digits where said forming function is based uponsuccessive assumed instant digits of 1 for said answer, means forsubtracting the first instant signal series from said number signals andfor storing electrical signals representing digits of the instantremainder and for subtracting successive instant signal series frompreceding instant remainder signals and for storing electrical signalsrepresenting digits of successive instant remainders, means fordetecting whether said instant remainder signals represent positive ornegative remainders, means responsive to the detection of an instantpositive remainder for storing an electrical signal representing aninstant digit 1 in said answer storing means and responsive to thedetection of an instant negative remainder for storing an electricalsignal representing an instant digit 0 in said answer storing means, andmeans responsive to the detection of an instant negative remainder forforming from said instant negative remainder signals electrical signalsrepresenting an X digit number equal to the proper next instantremainder commensurate with the instant registered answer digit of 0.

9. In a binary digital computer, a square router for extracting thesquare root of a number represented by X binary digits and comprisingmeans'for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe forming function is based upon successive assumed instant digits of1 for said answer, means for converting each instant signal series intoelectrical signals representing its twos complement, means for addingthe first instant series twos complement signals to said number signalsand for registering electrical signals representing the instant sum andfor adding successive instant series twos complement signals topreceding signal sums and for registering electrical signalsrepresenting successive instant sums, means for detecting whether saidinstant signal sums are positive or negative, means responsive to thedetection of an instant positive sum for storing an electrical signalrepresenting an instant digit 1 in said answer storing means andresponsive to the detection of an instant negative sum for storing anelectrical signal representing an instant digit 0 in said answer storingmeans, and means responsive to the detection of an instant negativesignal sum for forming from said instant negative signal sum electricalsignals representing an X digit number equal to the proper next instantsum commensurate with the instant registered answer digit of 0.

10. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, dual condition meansarranged when in its first condition to form successive instant seriesof electrical signals representing successive instant series of X digitswhere said forming function is based upon successive assumed instantdigits assass n 21 of 1 for said answer and arranged when in its secondcondition to form a special instant set of electrical signalsrepresenting a special instant variable set of X digits where saidlatter forming function is' based upon a digit of for said answer, meansoperative when said dual condition means is in its first condition forconverting each instant signal series into electrical signalsrepresenting its twos complement, means for adding the first instantseries twos complement signals to said number signals and forregistering electrical signals representing the instant sum and foradding successive instant series twos complement signals to precedingsignal sums and for registering electrical signals representingsuccessive instant sums, means for detecting whether said instant signalsums are positive or negative, means responsive to the detection of aninstant positive sum for setting said dual condition means into itsfirst condition and for storing an electrical signal representing aninstant digit 1 in said answer storing means and responsive to thedetection of an instant negative sum for setting said dual conditionmeans into its second condition and for storing an electrical signalrepresenting an instant digit 0 in said answer storing means, and meansincluding said dual condition means responsive to the detection of aninstant negative sum for forming from said instant negative signal sumelectrical signals representing an X digit number equal to the propernext instant sum by adding to said instant negative signal sum the saidspecial instant signal set of X digits.

11. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, a two- 'position switch,means operative when said switch is in its first position to formsuccessive instant series of electrical signals representing successiveinstant series of X instant digits where said forming function is basedupon successive assumed digits of 1 for said answer, means operativewhen said switch is in its second position to form a special instant setof electrical signals representing a special instant variable set of Xdigits where said latter forming function is based upon a digit of 0 forsaid answer, means operative when said switch is in its first positionfor converting each instant signal series into electrical signalsrepresenting its twos complement, means for adding the first instantseries twos complement signals to said number signals and forregistering electrical signals representing the instant sum and foradding successive instant series twos complement signals to precedingsignal sums and for registering electrical signals representingsuccessive instant sums, means for detecting whether said instant signalsums are positive or negative, means responsive to the detection of aninstant positive sum for setting said switch into its first position andfor storing an electrical signal representing an instant digit 1 in saidanswer storing means and responsive to the detection of an instantnegative sum for setting said switch into its second position and forstoring an electrical signal representing an instant digit 0 in saidanswer storing means, and means including said switch respon sive to thedetection of an instant negative sum for forming from said instantnegative signal sum electrical signals representing an X digit numberequal to the proper next instant sum by adding to said instant negativesignal sum the said special instant signal set of X digits.

' 12. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving elec-- trical signals representing the digits ofsaid number, means for storing electrical signals representing thedigits of the square root of said number as the answer, means forforming function is based upon successive associated assumed instantdigits of 1 for said answer, each instant signal series being of fixedsignal content depending upon the significance of the associated assumedinstant digit in said answer, means for subtracting the first instantsignal series associated with the most significant assumed instant digitof said answer from said number signals and for storing electricalsignals representing the instant remainder and for subtractingsuccessive instant signal series associated with successive significantassumed instant digits of said answer from said preceding remaindersignals and for storing electrical signals representing successiveinstant remainders, means for detecting whether said instant remaindersignals represent positive or negative remainders, means responsive tothe detection of an instant positive remainder for storing an electricalsignal representing an instant associated significant digit 1 in saidanswer storing means and responsive to thedetection of an instantnegative remainder for storing an electrical signal representing aninstant associated significant digit 0 in said answer storing means, andmeans responsive to the detection of an instant negative remainder forforming from said instant negative remainder signals electrical signalsrepresenting an X digit number equal to the next instant remaindercommensurate with the instant registered associated significant digit of0;

13. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, means for formingsuccessive instant series of electrical signals representing successiveinstant series of X digits where said forming function is based uponsuccessive associated assumed instant digits of 1 for said answer, eachinstant signal series being of fixed signal content depending upon thesignificance of the associated assumed instant digit in said answer,means for converting each instant signal series into electrical signalsrepresenting its twos complement, means for adding the first instantseries twos complement signals associated with the most significantassumed instant digit of said answer to said number signals and forregistering electrical signals representing the instant sum and foradding successive instant series twos complement signals associated withsuccessive significant assumed instant digits of said answer topreceding signal sums and for registering electrical signalsrepresenting successive instant sums, means for detecting whether saidinstant signal sums are positive or negative, means responsive to thedetection of an instant positive sum for storing an electrical signalrepresenting an instant associated significant digit 1 in said answerstoring means and responsive to the detection of an instant negative sumfor storing an electrical signal representing an instant associatedsignificant digit 0 in said answer storing means, and means responsiveto the detection of an instant negative sum for forming from saidinstant negative signal sum electrical signals representing an X digitnumber equal to the proper next instant sum commensurate with theinstant registered associated significant answer digit of 0.

14. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, dual condition meansarranged when in its first condition to form successive instant seriesof electrical signals representing successive instant series of X digitsWhere said forming function is based upon successive associated assumedinstant digits of 1 for said answer and arranged when in its secondcondition to form a special instant set of electrical signalsrepresenting a special instant variable set Of X digits where saidlatter forming function is based upon an associated assumed instantdigit of for said answer, each instant signal series being of fixedsignal content depending upon the significance of the associated assumedinstant digit in said answer, means operative when said dual conditionmeans is in its first condition for converting each instant signalseries into electrical signals representing its twos complement, meansfor adding the first instant series twos complement signals associatedwith the most significant assumed instant digit of said answer to saidnumber signals and for registering electrical signals representing theinstant sum and for adding successive instant series twos complementsignals associated with successive significant assumed instant digits ofsaid answer to preceding signal sums and for registering electricalsignals representing successive instant sums, means for detectingwhether said instant signal sums are positive or negative, meansresponsive to the detection of an instant positive sum for setting saiddual condition means into its first condition and for storing anelectrical signal representing an instant associated significant digit 1in said answer storing means and responsive to the detection of aninstant negative sum for setting said dual condition means into itssecond condition and for storing an electrical signal representing aninstant associated significant digit 0 in said answer storing means, andmeans including said dual condition means responsive to the detection ofan instant negative sum for forming from said instant negative signalsum electrical signals representing an X digit number equal to theproper next instant sum by adding to said instant negative signal sumthe said special instant signal set of X digits associated with theinstant significant digit 0.

15. In a binary digital computer, a square rooter for extracting thesquare root of a number represented by X binary digits and comprisingmeans for receiving electrical signals representing the digits of saidnumber, means for storing electrical signals representing the digits ofthe square root of said number as the answer, a two-position switch,means operative when said switch is in its first position to formsuccessive instant series of electrical signals representing successiveinstant series of X digits where said formingfunction is based uponsuccessive associated assumed instant digits of 1 for said answer, eachinstant signal series being of fixed signal content depending upon thesignificance of the associated assumed instant digit in saidanswer,means operative when said switch is in its second position to form aspecial instant set of electrical signals representing a specialvariable instant set 10f X digits where said latter forming ,functionis.based upon an associated significant instant digit of .0 for saidanswer, means operative when said switch is in its first condition forconverting each instant signal series into electrical signalsrepresenting its twos complement, means for adding the first instantseries twos complement signals associated with the most significantassumed instant digit of said answer to said number signals and forregistering electrical signals representing the instant sum and foradding successive instant series twos complement signals associated withsuccessive significant assumed instant digits of said answer topreceding signal sums and for registering electrical signalsrepresenting successive instant sums, means for detecting whether saidinstant signal sums are positive or negative,

means responsive to the detection of an instant positive sum for settingsaid switch into its first position and for storing an electrical signalrepresenting an instant associated significant digit 1 in said answerstoring means and responsive to the detection of an instant negative sumfor setting said switch into its second position and for storing anelectrical signal representing an instant associated significant digit 0in said answer storing means, and means including said switch responsiveto the detection of an instant negative sum for forming from saidinstant negative signal sum electrical signals representing an X digitnumber equal to the proper next instant sum by adding to said instantnegative signal sum the said special instant signal set of X digitsassociated with the instant significant digit 0 in said answer.

16. The invention defined in claim 15 wherein said answer is a W orderbinary number and wherein X represents a 2W order binary number.

References Cited in the file of this patent UNITED STATES PATENTS2,318,591 Coufiignal May 11, 1943 r 2,394,924 Luhn Feb. 12, 19462,493,862 Durfee Jan. 10, 1950 2,502,360 1950 Williams Mar. 28,

